1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a memory apparatus including nonvolatile memory cells.
2. Related Art
A known DRAM includes memory cells formed of capacitors and stores data while charging electric charges into the memory cells or discharging electric charges from the memory cells. However, the DRAM has a disadvantage of a volatile memory because the capacitor has a leakage current. In order to improve the disadvantage of the DRAM, nonvolatile memories not requiring the retention of data are being developed. In particular, attempts to implement a nonvolatile memory by changing the structure of a memory cell continue to be made. One of the attempts is a resistive memory apparatus including resistive memory cells.
FIG. 1 is a schematic diagram showing the construction of a known nonvolatile memory apparatus. Referring to FIG. 1, the known nonvolatile memory apparatus 10 includes a memory cell 11, a first transistor N1, a second transistor N2, a third transistor N3, a read sense amplifier 12, and a write driver 13. The memory cell 11 is made of a resistive material having a resistance value that varies depending on temperature or the amount of an electric current. The memory cell 11 has a different resistance value according stored data. Furthermore, the memory cell 11 includes a diode so that an electric current can flow in one direction.
The first transistor N1 couples the read sense amplifier 12 with the memory cell 11 in response to a bit line selection signal BLS supplied to the gate of the first transistor N1. The second transistor N2 couples the write driver 13 with the memory cell 11 in response to the bit line selection signal BLS. The third transistor N3 couples the is memory cell 11 with a terminal for a ground voltage VSS in response to a word line selection signal WLS, thus forming a current path to the memory cell 11.
The read sense amplifier 12 supplies a read current IRD in response to a read control signal RD. The write driver 13 supplies a write current IWT in response to a write control signal WT and data DATA. In response to the read control signal RD, the bit line selection signal BLS, and the word line selection signal WLS for a read operation, the read sense amplifier 12 supplies the read current IRD to the memory cell 11, senses voltage VSEN varying depending on a resistance value of the memory cell 11, and outputs data according to the sensed voltage. In response to the write control signal WT, the data DATA, the bit line selection signal BLS, and the word line selection signal WLS for a write operation, the write driver 13 supplies the write current IWT to the memory cell 11 so that a resistance value of the memory cell 11 is changed depending on the intensity of the write current IWT.
The read sense amplifier 12 and the write driver 13 have respective current mirror structures in order to generate the read current IRD and the write current IWT respectively. The current mirror consumes a large amount of an electric current and the current driving ability of the current mirror is changed depending on a position, thereby limiting the dispositions of the read sense amplifier 12 and the write driver 13. Furthermore, in a method of supplying the read current IRD and the write current IWT, data stored in the is memory cell 11 can be altered in a read operation because a peak current according to switching is generated, with the result that a possibility that data different from desired data can be stored in the memory cell 11 in a write operation is increased. Furthermore, the read sense amplifier 12 uses a first high voltage VPPSA to generate the read current IRD, and the write driver 13 uses a second high voltage VPPWD to generate the write current IWT. As a result, the amount of an electric current necessary to generate the first and the second high voltages VPPSA and VPPWD is increased.